Poly silicon layer and structure for forming the same

ABSTRACT

A method of fabricating a poly silicon layer comprising the following steps is provided. First, a substrate is provided and an amorphous silicon layer is formed on the substrate. A patterned metal layer is formed on the amorphous silicon layer. Next, a pulsed rapid thermal annealing process is performed to form a metal silicide between the patterned metal layer and the amorphous silicon layer, wherein the patterned metal layer and the amorphous silicon layer are adopted for conducting thermal energy to the amorphous silicon layer such that the amorphous silicon layer is converted into a polysilicon layer. Finally, the patterned metal layer is removed. A polysilicon layer formed according to the above-mentioned fabrication method is also provided. The grains of the poly silicon layer are spherical in shape.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of an application Ser. No. 11/308,961,filed on May 30, 2006. The entirety of the above-mentioned patentapplication is hereby incorporated by reference herein and made a partof this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a film and a structure forforming the same, and more particularly, to a polysilicon layer and astructure for forming the same.

2. Description of Related Art

A display serves as a communication interface for human to acquireinformation from a device, and the flat panel display (FPD) is thecurrent trend in the display market. The FPD can be classified intovarious types including an organic electro-luminescence display (OLED),a plasma display panel (PDP), a liquid crystal display (LCD), a lightemitting diode (LED) and so on.

The above-mentioned display usually employs the thin film transistor(TFT) as the switch of the display. Generally speaking, the TFT may beclassified into mainly two types including an amorphous silicon TFT anda low-temperature poly silicon thin film transistor (LTPS TFT). Comparedwith the conventional amorphous silicon TFT, since the electron mobilityof the LTPS TFT may exceed 200 cm2/V-sec, the area of the LTPS TFT issmaller to meet the requirement of high aperture ratio.

The poly silicon layer serving as the channel layer of the LTPS TFT maybe fabricated by the following methods.

1. Furnace annealing (FA) process combining with solid phasecrystallization (SPC)-the disadvantage of this method lies in that theoperation temperature is too high (more than 600° C.) and the requiredtime for the thermal process is too long (more than 15 hours). Besides,when using a glass substrate, the glass substrate is likely to becomedeformed due to the high temperature.

2. Excimer laser crystallization (ELA) process-the disadvantage of thismethod lies in that the equipment is more expensive, the processing timeis longer and the surface roughness of the poly silicon layer is poor.

3. Metal induced lateral crystallization (MILC) process-the disadvantageof this method lies in that the poly silicon film has metalcontamination. Besides, since the individual grain size is too small,the size of the grain can only be represented by the range value.

4. Rapid energy transfer annealing (RETA) process-the disadvantage ofthis method lies in that the process adopts a wafer as a heating plate,and therefore this method may not be applied to the large-sizedsubstrate.

SUMMARY OF THE INVENTION

The present invention is also directed to a polysilicon layer havingcomparatively larger grains size.

As embodied and broadly described herein, the present invention isdirected to a method of fabricating a polysilicon layer comprising thefollowing steps. First, a substrate is provided and an amorphous siliconlayer is formed on the substrate. A patterned metal layer is formed onthe amorphous silicon layer. Next, a pulsed rapid thermal annealing(PRTA) process is performed to form a metal silicide between thepatterned metal layer and the amorphous silicon layer, and the patternedmetal layer and the metal silicide are adapted for conducting thermalenergy to the amorphous silicon layer such that the amorphous siliconlayer is converted into a polysilicon layer. Finally, the patternedmetal layer is removed.

According to an embodiment of the present invention, a material of thepatterned metal layer comprises nickel, cobalt, copper, tantalum, ironor platinum.

According to an embodiment of the present invention, an operationtemperature of the pulsed rapid thermal annealing process is between550° C. and 900° C.

As embodied and broadly described herein, the present invention alsoprovides a polysilicon layer formed according to the above-mentionedfabrication method. The grains of the poly silicon layer are sphericalin shape.

According to an embodiment of the present invention, the grain size islarger than 4000 angstrom.

According to an embodiment of the present invention, the surfaceroughness of the poly silicon layer is smaller than 10 angstrom.

In accordance with the foregoing descriptions, the present inventionemploys the pulsed rapid thermal annealing process for forming the metalsilicide and the patterned metal layer and the amorphous silicon layermay conduct thermal energy to the amorphous silicon layer to transformthe amorphous silicon layer into a polysilicon layer. Compared with theconventional MILC, since the metal silicide of the present invention isnot likely to laterally migrate, the occurrence of the metalcontamination may be effectively reduced. In addition, compared with theconventional ELA process, the fabrication method provided by presentinvention may manufacture poly silicon layers with comparatively largergain size.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIGS. 1A to 1F are schematic, cross-sectional diagrams illustrating theprocess flow for fabricating a poly silicon layer according to anembodiment of the present invention.

FIG. 2 is a diagram showing a heating curve of the PRTA processaccording to an embodiment of the present invention.

FIG. 3 is a spectrum diagram of the poly silicon layer measured by anenergy dispersive X-ray spectrometer.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

FIGS. 1A to 1F are schematic cross-sectional diagrams illustrating theprocess flow for fabricating a poly silicon layer according to anembodiment of the present invention. Referring to FIG. 1A, the method offabricating a polysilicon layer according to an embodiment of thepresent invention comprises the following steps. First, a substrate 110is provided, and the substrate 110 may be a glass substrate or a quartzsubstrate. Next, an amorphous silicon layer 120 is formed on thesubstrate 110. The amorphous silicon layer 120 may be formed using, forexample, a chemical vapor deposition (CVD) process or a plasma enhancedCVD (PECVD) process.

Referring to FIG. 1B, a metal layer 130 is formed on the amorphoussilicon layer 120, and the metal layer 130 may be comprised of nickel,cobalt, copper, tantalum, iron, platinum or any other metallic materialand may be formed by using, for example, a sputtering process.

Referring to FIG. 1C, a portion of the metal layer 130 is removed toform a patterned metal layer 132. A portion of the metal layer 130 maybe removed by using, for example, a photolithography process and anetching process.

Referring to FIG. 1D, a PRTA process is performed to form a metalsilicide 140 between the patterned metal layer 132 and the amorphoussilicon layer 120. Next, during the PRTA process, the patterned metallayer 132 and the metal silicide 140 conduct thermal energy to theamorphous silicon layer 120 such that the amorphous silicon layer 120 istransformed into a polysilicon layer 150 as shown in FIG. 1E.

FIG. 2 is a diagram showing a heating curve of the PRTA processaccording to an embodiment of the present invention. Referring to FIGS.1D and 2, the horizontal coordinate represents time, wherein a unit oftime is one second, and the vertical coordinate represents temperature,wherein centigrade represents the units used for the degrees oftemperature. For example, the operation temperature of the PRTA processis between 550° C. and 900° C. In addition, for each cycle, the hightemperature (900° C.) lasts for 5 seconds, the slope for heating is 70°C./second and the slope for cooling is 35° C./second. More specifically,a seed metal silicide 140 serving as crystal seed may be formed inadvance. Next, infra red energy generated from the PRTA process isconverted to heat by the metal silicide 140 and the patterned metallayer 132, and then heat is conducted to the amorphous silicon layer 120to make it crystallize. In other words, the mechanism ofre-crystallization is a kind of SPC-like method.

Referring to FIG. 1F, the patterned metal layer 132 is removed, and thepatterned metal layer 132 may be removed by an etching process. Thus,the method of fabricating the polysilicon layer 150 according to anembodiment of the present invention is complete.

Since the conventional MILC process utilizes the lateral migration ofthe metal silicide to induce the amorphous silicon layer tore-crystallize, and therefore the lateral crystallization region (aregion which is not covered by the patterned metal layer 132 shown inFIG. 1D) may have metal contamination. The poly silicon layer isanalyzed by an energy dispersive X-ray spectrometer (EDS), and theresult is shown as follows.

FIG. 3 is a spectrum diagram of the poly silicon layer measured by anenergy dispersive X-ray spectrometer. Referring to FIG. 3, thehorizontal coordinate represents energy, wherein a unit of energy is onekiloelectron volt (KeV), and the vertical coordinate represents countsper second (cps). The metal silicide of the present invention may notmigrate laterally, and therefore the signal of nickel within the lateralcrystallization region is not obvious (such as the dotted line region inFIG. 3). In other words, the lateral crystallization region hasnegligible amount of nickel.

Referring to FIG. 1F, the grains of the poly silicon layer formed by theconventional ELA process, are arborization. However, the grains of thepoly silicon layer 150 formed according to the above-mentioned processesare substantially spherical in shape. Since the metal silicide makes thegeneration of a portion of the nucleation sites earlier, therefore thenucleation density is significantly reduced and the polysilicon layer150 has larger grains size. Compared to the size of the grains of thepoly silicon layer formed by the conventional ELA process, which isabout 3000 angstrom to 4000 angstrom, the size of the grains of thepolysilicon layer formed according to the above-mentioned processes maybe larger than 4000 angstrom. Besides, compared to the surface roughnessof the poly silicon layer formed by the conventional ELA process isbetween dozens to hundreds of nanometers, but the surface roughness ofthe polysilicon layer formed by the above-mentioned process may besmaller than 10 angstrom.

In summary, the present invention has at least the following advantages.

1. Compared to the conventional SPC process, the present invention isfaster (less than 2 minutes). The present invention employs the PRTAprocess, and accordingly it is suitable for forming a polysilicon layeron every kind of substrate.

2. Compared to the conventional ELA process, the equipment required bythe present invention is cheaper and the processing time thereof isfaster (less than 2 minutes). Additionally, the planarity of thepolysilicon layer formed according to the present invention is better,which is less than 10 angstrom.

3. Compared with the conventional MILC process, the metal contaminationof the present invention may not migrate laterally, and therefore themetal contamination may be effectively avoided.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A poly silicon layer, comprising; a substrate; and a poly silicon layer on the substrate, wherein grains of the polysilicon layer are spherical in shape.
 2. The poly silicon layer according to claim 1, wherein a size of the grain is larger than 4000 angstrom.
 3. The poly silicon layer according to claim 1, wherein a surface roughness of the poly silicon layer is smaller than 10 angstrom.
 4. The poly silicon layer according to claim 1, further comprising a patterned metal layer on the poly silicon layer.
 5. The poly silicon layer according to claim 4, wherein a material of the patterned metal layer comprises nickel, cobalt, copper, tantalum, iron or platinum.
 6. A structure for forming a poly silicon layer, comprising; a substrate; an amorphous silicon layer on the substrate; a patterned metal layer on the amorphous silicon layer; and a metal silicide between the patterned metal layer and the amorphous silicon layer.
 7. The structure according to claim 6, wherein a material of the patterned metal layer comprises nickel, cobalt, copper, tantalum, iron or platinum.
 8. The structure according to claim 6, wherein the metal silicide is formed on the surface of the amorphous silicon layer and does not pass through the amorphous silicon layer. 